1. Field of the Invention
The invention relates in general to the method of fabricating a semiconductor device, and more particularly to the method of fabricating a self-align-contact with low resistance.
2. Description of the Related Art
In the semiconductor process there are many methods of fabricating a self-align-contact. One of conventional methods of forming a self-align-contact includes first providing a substrate on which there are at least two MOS devices and then forming an insulating layer, such as silicon oxide, on the substrate. Each of the two MOS devices includes a polysilicon gate and spacers on the sidewalls of the gate. The two MOS devices have a common source/drain region located between the gates of the two MOS devices. The insulating layer is patterned to form a self-align-contact opening to expose the common source/drain region. A conductive layer is deposited in the self-align-contact opening to form a self-align-contact of prior art.
A process flow showing the formation of a conventional self-align-contact is illustrated by FIGS. 1A-1D. Referring to FIG. 1A, a gate 102 and source/drain regions 110 are formed on a semiconductor substrate 100. The gate 102 includes a gate oxide 104, a doped polysilicon layer 106 and a cap layer 108. The cap layer 108 is formed over the doped polysilicon layer 106 to protect the doped polysilicon layer 106. A spacer 112 is formed on the sidewalls of the gate 102. The source/drain regions 110 are lightly doped drain (LDD) structures. The method of forming the source/drain regions 110 includes lightly implanting ions into the semiconductor substrate 100 using the gate 102 as a mask and heavily implanting ions into the semiconductor substrate 100 using the spacer 112 as a mask. Referring to FIG. 1B, a dielectric layer 114 is formed on the semiconductor substrate 100 by CVD.
Next, referring to FIG. 1C, the dielectric layer 114 is patterned by both a lithography process and by etching to form a contact opening 116 between two gates 102 to expose the source/drain region 110. When etching the dielectric layer 114, the spacer 114a is naturally formed on the spacer 112. Therefore, the spacer structure on the sidewalls of the gate 102 has a large width, including the width of the spacer 114a and the width of the spacer 112.
Next, referring to FIG. 1D, a conductive layer 118, such as doped polysilicon, is deposited in the contact opening 116 and on the semiconductor substrate 100. The conductive layer 118 is patterned to form a self-align-contact of prior art.
In the integrated circuits (IC) process, the conventional method of fabricating a self-align-contact includes many drawbacks. For example, the width of the self-align-contact is very large. As shown in FIG. 1C, the spacer 114a reduces the exposed surface of the source/drain regions 110 from the length X to the length Y. The reduction of the exposed area of the source/drain regions 110 increases the resistance of the self-align-contact and cannot meet the needs of current integrated circuits with high operation speed.